The present invention relates to a solid-state imaging device and, more particularly, to a reset voltage setting circuit for setting the reset voltage to be applied to a signal charge detecting section for detecting signal charges when the section is reset.
FIG. 1 schematically shows the overall arrangement of a solid-state imaging device 100 to which the present invention can be applied. The solid-state imaging device 100 comprises a photosensitive area 105, a horizontal transfer CCD (Charge-Coupled Device) 103, and an output area 104. The photosensitive area 105 has photosensitive pixels 101 two-dimensionally arranged in the vertical direction in FIG. 1, and vertical transfer CCDs 102 adjacent to the photosensitive pixels 101. The photosensitive pixels 101 generate signal charges upon irradiation of light. The photosensitive pixels 101 store the signal charges and output them to the vertical transfer CCDs 102. The vertical transfer CCDs 102 transfer the supplied signal charges in the vertical direction in accordance with the timing of a transfer pulse.
The signal charges transferred by the vertical transfer CCDs 102 are transferred by the horizontal transfer CCD 103 in the horizontal direction. The signal charges transferred by the horizontal transfer CCD 103 are supplied to the output area 104. The output area 104 includes a floating diffusion layer, a source follower circuit, a reset gate, and a reset drain. The floating diffusion layer stores the signal charges transferred from the horizontal transfer CCD 103. The source follower circuit converts the stored signal charges into a voltage signal. Upon reception of a reset pulse, the reset gate transfers the signal charges stored in the floating diffusion layer to the reset drain.
FIG. 2 shows the arrangement of the reset voltage setting circuit of a conventional charge detecting section. Signal charges are generated by pixels and sequentially transferred by a CCD register. The signal charges are then transferred to a floating diffusion layer 1 through an output gate OG set at a predetermined voltage and temporarily stored. The floating diffusion layer 1 consists of a diffusion layer having a conductivity type opposite to that of a semiconductor substrate, and is formed at a predetermined distance from a reset drain diffusion layer 2 having the same conductivity type as that of the floating diffusion layer 1 through a channel region doped with a predetermined concentration of an impurity having the same conductivity type as that of the floating diffusion layer 1. A reset gate electrode is formed on the channel region through an insulating film (not shown). The floating diffusion layer 1, the channel region, the reset drain diffusion layer 2, and the reset gate electrode constitute a depletion-type (to be referred to as a D-type hereinafter) MOS transistor, which operates as a reset transistor 3.
A source follower circuit 9 is connected to the floating diffusion layer 1. In the source follower circuit 9, an N-channel transistor 10 and a D-type transistor 11 serving as a resistive element are series-connected between a power supply voltage terminal Vcc and the ground terminal, and the gate of the transistor 10 is connected to the floating diffusion layer 1. The node between one end of the transistor 10 and one end of the transistor 11 is connected to an output terminal 12.
The signal charges stored in the floating diffusion layer 1 are converted into a voltage signal by the source follower circuit 9. The voltage signal is then output from the output terminal 12.
An external capacitor 4 is connected to the reset gate electrode. A reset pulse is applied from a reset terminal 5 to the reset gate electrode through the external capacitor 4. A power supply 8 is connected to the reset drain 2, to which a reset drain voltage VRD is applied. A voltage dividing circuit 7 is connected between the reset drain 2 and the reset gate electrode to perform a normal reset operation by canceling out setting variations of the reset drain voltage VRD. In the voltage dividing circuit 7, resistors R1 and R2 are series-connected between the reset drain 2 and the ground terminal, and the node between the resistors R1 and R2 is connected to the reset gate electrode of said reset section. In this case, the resistors R1 and R2 consist of diffused resistors. With this voltage dividing circuit 7, a voltage VRS obtained by resistively dividing the voltage VRD of the power supply 8 is applied to the reset gate electrode.
The level of a reset pulse for a normal reset operation will be described next. The potential at the region under the gate electrode of the reset transistor 3 upon application of a high-level reset pulse must be higher than the voltage VRD of the power supply 8.
Assume that the potential at the region beneath the gate electrode upon application of a high-level reset pulse is higher than the voltage VRD by a reset transfer margin .PHI.2. In order to allow the source follower circuit 9 to output a detection voltage of about 1.5 V or more, signal charges must be stored in the floating diffusion layer 1 in a predetermined quantity or more. For this purpose, a voltage lower than the voltage VRD by a reset barrier margin .PHI.1 must be generated at the region underneath the gate electrode. As described above, the potential at the region under the gate electrode must be higher than the voltage VRD by the reset transfer margin .PHI.2 upon application of a high-level reset pulse, and lower than the voltage VRD by the reset barrier margin .PHI.1 upon application of a low-level reset pulse.
FIG. 3 shows the relationship between the voltage VRS and the currents flowing in the resistors R1 and R2 in the voltage dividing circuit 7. A curve L11 represents changes in the current flowing in the resistor R1 with changes in the voltage VRS. As the current flowing the resistor R1 decreases, the voltage VRS rises. A curve L12 represents changes in the current flowing in the resistor R2 with changes in the voltage VRS. As the current flowing in the resistor R2 increases, the voltage VRS rises. The intersection point of the curves L11 and L12 corresponds to the value of the voltage VRS in this circuit.
A curve L13 represents the relationship between the voltage VRS and the current flowing in the resistor R1 when the voltage VRD of the power supply 8 increases by .DELTA.VRD. As the voltage VRD rises, the voltage VRS rises if the current flowing in the resistor R1 remains the same. The intersection point of the curves L12 and L13 indicates the value of the voltage VRS when the voltage VRD rises by .DELTA.VRD. The voltage VRS rises by .DELTA.VRS.
The value .DELTA.VRS is smaller than the value .DELTA.VRD, and the value of .DELTA.VRS/.DELTA.VRD is about 0.8. This is because the current flowing in the resistor R2 changes as the voltage VRD varies. The ratio of the variation in the potential at the region beneath the reset gate electrode to the variation .DELTA.VRD is about 0.7.
In addition, the reset transfer margin .PHI.2 must be set to a voltage high enough to absorb the variation .DELTA.VRD in the voltage VRD of the power supply 8 and the variation in the potential at the region under the reset gate electrode. For example, the reset transfer margin .PHI.2 must be set to 1.5 V. The potential at the region under the reset gate varies due to variations in impurity concentration. However, this variation is not fed back to the voltage VRS. This is because, even if the impurity concentration of the region under the reset gate varies, the resistances of the resistors R1 and R2 do not vary in the same manner. For this reason, such a variation in the potential at the region underneath the reset gate must be included in the reset transfer margin .PHI.2.
Similar to the reset transfer margin .PHI.2, as the reset drain voltage VRD varies, the reset barrier margin .PHI.1 varies through the voltage dividing circuit 7. Even if, however, the reset gate potential varies, the reset gate voltage VRS does not vary. For this reason, this variation in the reset gate potential must be included in the reset barrier margin .PHI.1 as well. As a result, the reset barrier margin .PHI.1 must be set to a high voltage, e.g., 2.5 V, which is obtained when the potential variation at the region under the reset gate is included in the voltage required to detect signal charges.
The potential width in the region under the reset gate must be set to 3.5 V or more, which is the sum of the margins .PHI.1 and .PHI.2. That is, a voltage of about 4 V is required in terms of the voltage VRS to be applied to the reset gate.
As described above, in the conventional charge detecting section, when the potential at the region under the reset gate varies owing to variations in impurity concentration under the reset gate in the manufacturing process, no similar variation is fed back to the circuit for generating the voltage to be applied to the reset gate. For this reason, a pulse having a large amplitude must be applied to the reset gate. The power consumption therefore increases, and a low power supply voltage of about 3.3 V used for peripheral circuits cannot be used.